ARM Processor Architecture MCQ Questions and Answers for Practice

1. The memory blocks in Main Memory are mapped on to the cache blocks with the help of

1. Hash functions
2. Vectors
3. Mapping functions
4. None of the above

2. The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called

1. Level 1 cache
2. MMU
3. Registers
4. TLB

3. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

1. Set associative
2. Associative
3. Direct
4. Indirect

4. The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB

1. Master and slave
2. Master and master
3. Slave and slave
4. None of the above

5. The priority of a process will.........if the scheduler assigns it a static priority.

1. change
2. remain unchanged
3. depend on the operating system
4. None of the above

6. The two I2C signals are..........and............

1. Serial data, serial clock
2. Serial select, serial access
3. Serial address, parallel data
4. Parallel address, Parallel clock

7. Thumb-2 technology enhances the 16 bit Thumb instruction set with

1. Intermixing of 32 bits and 16 bits instructions
2. Only 32 bits instructions
3. Only 16 bits instructions
4. None of the above

8. Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

1. ADD r4, r0, r2 ; ADC r5, r1, r3 ;
2. ADDS r4, r0, r2 ; ADCS r5, r1, r3 ;
3. ADD r4, r0, r2 ; ADD r5, r1, r3 ;
4. ADD r4, r0, r2 ; ADCS r5, r1, r3 ;

9. Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........

1. Instruction bandwidth and Data hazard checking
2. Instruction bandwidth and pipelining
3. Data Hazard checking and pipelining
4. All of the above

10. Vector Floating Point (VFP) architecture provides............floating point architectures.

1. Single precision
2. Double precision
3. Both a and b
4. None of the above

11. Vector processor architecture falls under the following computer architecture

1. SISD
2. MIMD
3. SIMD
4. MISD

12. What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101

1. i) R2 = 0x01010101 ii) R1 = 0x01010101
2. i) R2 = 0x01010101 ii) R1 = 0x10101010
3. i) R2 = 0x10101010 ii) R1 = 0x01011101
4. i) R2 = 0x01100110 ii) R1 = 0x01010101

13. What is inter-process communication?

1. Communication within the process
2. Communication between two processes
3. Communication between two threads of same process
4. None of the above

14. When a global variable may be modified by an exception handler, it should be declared as:

1. Constant
2. Static
3. Dynamic
4. Volatile

15. When a page is selected for replacement, and its modify bit is set :

1. the page is clean
2. the page has been modified since it was read in from the disk
3. the page is dirty
4. a and b