ARM Processor Architecture Quiz | ARM Processor Architecture Question and Answer for Practice

31. ..........is the concept in which a process memory is copied into the main memory from the secondary memory according to the requirement.

1. Segmentation
2. Swapping
3. Paging
4. Demand paging

32. “Write Back” cache write policy is more efficient in a system where

1. Does not depend on the number of reads and writes
2. None of the above
3. Number of writes are more than reads
4. Number of reads are more than writes

33. A band limited signal can be reconstructed exactly if it is sampled at a rate at least

1. Thrice the maximum frequency
2. All of the above
3. Maximum frequency
4. Twice the maximum frequency

34. A bus cycle request that transfers to or from an address which is unrelated to the address used in the preceding cycle is called a

1. Non-Sequential Cycle
2. Coprocessor Register Transfer Cycle
3. Sequential Cycle
4. Internal Cycle

35. A CPU wrote „register content‟ into the memory in a Big-endian mode. When the same content is read back from the memory into a register, the CPU reads it in Little-endian mode.

1. The content may be same or different.
2. Endianness need not be the same while reading and writing the contents into/from the memory.
3. The new content in the register will be different from what was written.
4. The content will be the same.

36. A data processing instruction where PC(R15)is written into takes the following cycles for execution:

1. 2S+1N
2. 2S+1N+1I
3. 1S
4. 1S+I

37. A Page Table contains information on the page including

1. Page was written into or not
2. All of the above
3. Base address of each page in physical memory
4. Page read/write permissions

38. A process is thrashing if

1. page fault occurs very infrequently
2. swapping could not take place
3. it is spending more time paging management than executing
4. it is spending less time paging than executing

39. A scheduling algorithm can use either..........priority or..........priority.

1. live, dead
2. None of the above
3. static, still
4. static, dynamic

40. A virtual memory system uses „First In First Out‟ (FIFO) page replacement policy and allocates a fixed number of frames to a process. Consider the following tatements:
P: Increasing the number of page frames allocated to a process sometimes increases the page fault rate
Q: Some programs do not exhibit locality of reference which of the following is TRUE?

1. P is false but Q is true
2. Both P and Q are false
3. Both P and Q are true, and Q is the reason for P
4. Both P and Q are true, but Q is not the reason for P

41. An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called

1. MSR
2. MCS
3. MRC
4. MRS

42. By default DMA is not a

1. Clock
2. All of the above
3. Master
4. Slave

43. Cache design elements are

1. Mapping functions
2. All of the above
3. Block size
4. Cache size

44. Cache memory acts between

1. MMU and Hard Disk
2. None of these
3. CPU and Main Memory
4. CPU and FPU

45. Choose the correct order for default memory map

1. RO->RW->ZI
2. RO->ZI->RW
3. RW->RO->ZI
4. ZI->RO->RW