ARM Processor Architecture Questions and Answers | Online Quiz for Practice

46. Coherence means

1. Multiple copies of different data are available at only one level of hierarchy.
2. Multiple copies of different data are not available at each level of hierarchy.
3. Multiple copies of same data are available at each level of hierarchy.
4. Single copy of data is available at only one level of hierarchy.

47. Consider a four bit ALU which does four bit arithmetic. When the following four bit numbers are added, what is the status of NZCV flags? 1101 + 1011

1. NZCV = 1010
2. NZCV = 0111
3. NZCV = 1000
4. NZCV = 1001

48. Control signals can be categorized by the pipeline stage that uses them. Which one of the following signal could be used in the Execution stage of an instruction?

1. PCsrc
2. MemRead
3. RegWrite
4. ALUop

49. ELF means

1. None of the above
2. External Library Format
3. Executable and Linkable Format
4. Exclusive Loadable Format

50. Equivalent of Rd = NOT(Rm) this operation is performed by which instruction

1. TST
2. MVN
3. NEG
4. EOR

51. Evaluate the following statements and select the appropriate answer given from the choices below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions

1. None of them is true
2. Only I is true
3. Only II is true
4. Both I and II are true

52. Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched

1. I and III are true
2. All the options are true
3. I and II are true
4. II and III are true

53. Exponent and fraction values for a denormalized number are

1. 0, Any non-zero bit pattern
2. 0, 0
3. 0 < E < Max, Any bit pattern
4. All 1?s, Any bit pattern

54. Frequency of sampling is called

1. All of the above
2. Sampling rate
3. Quantization
4. Modulation

55. How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

1. None of the above
2. Faster
3. Slower
4. No difference

56. How many bits are required to specify the Register operands in anARM7 instruction?

1. 2 bits
2. 32 bits
3. 16 bits
4. 4 bits

57. I2C master features:

1. All of the above
2. Programmable I2C address detection
3. Clock generation
4. Stop bit detection

58. If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

1. 4 cycles
2. 12 cycles
3. 6 cycles
4. 9 cycles

59. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........

1. 250mS and 1500mS
2. 250 nS and 1500 nS
3. 250mS and 150 nS
4. 25 nS and 1500nS

60. If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?

1. MUL
2. AND
3. ORR
4. BIC