ARM Processor Architecture Quizzes | Trivia Quiz for Practice

76. Run time mapping from virtual to physical address is done by

1. Memory Management Unit
2. CPU
3. PCI
4. None of the above

77. Serial Peripheral Interface bus allows

1. Half/full
2. Synchronous
3. Serial communication with external devices
4. All of the above

78. Size of L1 cache compared to that of L2 cache in a system is

1. Higher
2. Lower
3. Same
4. None of the above

79. Stack is a form of

1. Last In First Out (LIFO)
2. First In First Out (FIFO)
3. Both a and b
4. None of the above

80. State whether the following statement is either true or false. A high performance bus can be connected to a low performance bus without bridge.

1. True Statement
2. False Statement

81. State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.

1. True Statement
2. False Statement

82. State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.

1. True Statement
2. False Statement

83. State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.

1. True Statement
2. False Statement

84. State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.

1. True Statement
2. False Statement

85. State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.

1. True Statement
2. False Statement

86. State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.

1. True Statement
2. False Statement

87. State whether the following statement is either true or false. Interrupt signal can stop the execution of an assembly instruction in the middle while it is being executed.

1. False Statement
2. True Statement

88. State whether the following statement is either true or false. Mantissa and exponent will improve the range and precision respectively.

1. True Statement
2. False Statement

89. State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie

1. This instruction branches to the initialization code.
2. True Statement
3. False Statement

90. State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.

1. True Statement
2. False Statement