ARM Processor Architecture Questions and Answers in Quiz Form 7 for Practice

91. State whether the following statement is either true or false. We can represent any number in more than one normalized notation.

1. True Statement
2. False Statement

92. Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9

1. Z = 1
2. Z = 0
3. Same as previous value
4. None of the above

93. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to

1. the time it takes for the platter to make a full rotation
2. the time it takes for the read-write head to move into position over the appropriate track
3. the time it takes for the platter to rotate the correct sector under the head
4. none of the above

94. The average time required to reach a storage location in memory and obtain its contents is called

1. Latency time
2. Access time
3. Turnaround time
4. Response time

95. The fastest data access is provided using

1. Caches
2. DRAM?s
3. SRAM?s
4. Registers

96. The idea of cache memory exploits the following property of programs

1. Principle of locality
2. on the heuristic 90-10 rule
3. on the fact that references generally tend to be farther
4. all of the above

97. The L1 cache is typically split into.........and...........cache for the pipelined system

1. Instruction, Data
2. Instruction, Instruction
3. Data, Data
4. All of the above

98. The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?

1. Since V flag and C flag are always the same after any logical operations
2. Because it will delay the execution of logical operations
3. V flag is relevant only when an Arithmetic operation is performed
4. None of the above

99. The main advantage of multiple bus organization over the single bus is

1. Reduction in the number of cycles for execution
2. Increase in size of the register
3. Better connectivity
4. None of the above

100. The MCLK speed can be reduced to allow access to

1. Faster peripherals
2. Slower peripherals
3. CPU
4. All of the above