Central Processing Unit CPU Questions and Answers | Online Quiz for Practice

46. The periods of time when the unit is idle is called as

1. Stalls
2. Bubbles
3. Hazards
4. Both Stalls and Bubbles

47. The pipelining process is also called as

1. Superscalar operation
2. Assembly line operation
3. Von Neumann cycle
4. None of the mentioned

48. The RISC processor has a more complicated design than CISC.

1. TRUE Statement
2. FALSE Statement

49. The situation wherein the data of operands are not available is called

1. Structural hazard
2. Stalk
3. Deadlock
4. Data hazard

50. The Sun micro systems processors usually follow............architecture.

1. CISC
2. ISA
3. ULTRA SPARC
4. RISC

51. To evaluate an expression using stack based instrcutions, expression is first converted into

1. prefix
2. infix
3. postfix
4. none of these

52. To increase the speed of memory access in pipelining, we make use of

1. Special memory locations
2. Special purpose
3. registers Cache
4. Buffers

53. Two main types of branch instructions are

1. conditional branch
2. unconditional branch
3. logical branch
4. both a and b

54. Which addressing mode is efficient

1. Immediate
2. Register
3. Indirect
4. Direct

55. Which of the following is not a visible register?

1. General Purpose Registers
2. Address Register
3. Status Register
4. MAR

56. zero address instruction also called as

1. stack based
2. accumulator based
3. can be a or b
4. none of these

57. Zero address instruction takes data from

1. top of the stack
2. front of the queue
3. can be a or b
4. none of these