Computer Architecture Multiple Choice Questions and Answers for Practice

16. The disadvantage of the EPROM chip is

1. The high cost factor
2. The low efficiency
3. The low speed of operation
4. The need to remove the chip physically to reprogram it

17. The drawback of building a large memory with DRAM is

1. The large cost factor
2. The inefficient memory organization
3. The Slow speed of operation
4. All of the mentioned

18. The effective address of the following instruction is MUL 5(R1,R2).

1. 5+R1+R2
2. 5+(R1*R2)
3. 5+[R1]+[R2]
4. 5*([R1]+[R2])

19. The fastest data access is provided using

1. Caches
2. DRAMs
3. SRAMs
4. Registers

20. The fetch and execution cycles are interleaved with the help of

1. Modification in processor architecture
2. Clock
3. Special unit
4. Control unit

21. The main advantage of multiple bus organization over a single bus is

1. Reduction in the number of cycles for execution
2. Increase in size of the registers
3. Better Connectivity
4. None of the mentioned

22. The main memory in a personal computer is made of

1. Static RAM
2. Both c and d
3. Cache memory
4. Dynamic RAM

23. The main virtue for using single Bus structure is

1. Fast data transfers
2. Cost effective connectivity and speed
3. Cost effective connectivity and ease of attaching peripheral devices
4. None of the mention

24. The memory blocks are mapped on to the cache with the help of

1. Hash functions
2. Vectors
3. Mapping functions
4. None of the mentioned

25. The method of accessing the I/O devices by repeatedly checking the status flags is

1. Program-controlled I/
2. Memory-mapped I/O
3. I/O mapped
4. None of the mentioned

26. The method of mapping the consecutive memory blocks to consecutive cache blocks is called

1. Set associative
2. Associative
3. Direct
4. Indirect

27. The method of synchronizing the processor with the I/O device in which the device sends a signal when it is ready is?

1. Exceptions
2. Signal handling
3. Interrupts
4. DMA

28. The method which offers higher speeds of I/O transfers is

1. Interrupts
2. Memory mapping
3. Program-controlled I/O
4. DMA

29. The minimum time delay between two successive memory read operations is

1. Cycle time
2. Latency
3. Delay
4. None of the mentioned

30. The multiplicand and the control signals are passed through to the n-bit adder via

1. MUX
2. DEMUX
3. Encoder
4. Decoder