Digital Electronics Quiz | Digital Electronics Question and Answer for Practice

31. The output of an OR gate is LOW when ________.

1. Any input is LOW
2. Any input is HIGH
3. All inputs are HIGH
4. All inputs are LOW

32. The Ex-NOR is sometimes called the ________.

1. Parity gate
2. Equality gate
3. Inverted OR
4. Parity gate or the equality gate

33. A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):

1. Ex-NOR gate
2. OR gate
3. Ex-OR gate
4. NAND gate

34. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

1. A = 1, B = 1, C = 0
2. A = 0, B = 0, C = 0
3. A = 1, B = 1, C = 1
4. A = 1, B = 0, C = 1

35. When used with an IC, what does the term "QUAD" indicate?

1. 2 circuits
2. 4 circuits
3. 6 circuits
4. 8 circuits1

36. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.

1. A = 0, B = 0, C = 0
2. A = 0, B = 0, C = 1
3. LA = 0, B = 1, C = 1
4. All of the above

37. Which of the following logical operations is represented by the + sign in Boolean algebra?

1. Inversion
2. AND
3. OR
4. Complementation

38. Output will be a LOW for any case when one or more inputs are zero for a(n):

1. OR gate
2. NOT gate
3. AND gate
4. NOR gate

39. A basic multiplexer principle can be demonstrated through the use of a:

1. Single-pole relay
2. DPDT switch
3. Rotary switch
4. Linear stepper

40. One multiplexer can take the place of:

1. Several SSI logic gates
2. Combinational logic circuits
3. Several Ex-NOR gates
4. Several SSI logic gates or combinational logic circuits

41. The inputs/outputs of an analog multiplexer/demultiplexer are:

1. Bidirectional
2. Unidirectional
3. Even parity
4. Binary-coded decimal

42. One application of a digital multiplexer is to facilitate:

1. Data generation
2. Serial-to-parallel conversion
3. Parity checking
4. Data selector

43. How many select lines would be required for an 8-line-to-1-line multiplexer?

1. 2
2. 3
3. 4
4. 8

44. Which of the following is correct for a gated D-type flip-flop?

1. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
2. The output complement follows the input when enabled
3. Only one of the inputs can be HIGH at a time
4. The output toggles if one of the inputs is held HIGH

45. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

1. If both inputs are HIGH, the output will toggle
2. The output will follow the input on the leading edge of the clock
3. When both inputs are LOW, an invalid state exists
4. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock