Digital Electronics Questions and Answers | Online Quiz for Practice

46. Which of the following is correct for a D latch?

1. The output toggles if one of the inputs is held HIGH
2. Q output follows the input D when the enable is HIGH
3. Only one of the inputs can be HIGH at a time
4. The output complement follows the input when enabled

47. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

1. CLK = NGT, D = 0
2. CLK = PGT, D = 0
3. CLOCK NGT, D = 1
4. CLOCK PGT, D = 1

48. A positive edge-triggered D flip-flop will store a 1 when ________

1. the D input is HIGH and the clock transitions from HIGH to LOW
2. the D input is HIGH and the clock transitions from LOW to HIGH
3. the D input is HIGH and the clock is LOW
4. the D input is HIGH and the clock is HIGH

49. If an input is activated by a signal transition, it is ________

1. edge-triggered
2. toggle triggered
3. clock triggered
4. noise triggered

50. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

1. AND or OR gates
2. XOR or XNOR gates
3. NOR or NAND gates
4. AND or NOR gates

51. One example of the use of an S-R flip-flop is as a(n)

1. Transition pulse generator
2. Astable oscillator
3. Racer
4. Switch debouncer

52. If both inputs of an S-R NAND latch are LOW, what will happen to the output?

1. The output would become unpredictable
2. The output will toggle
3. The output will reset
4. No change will occur in the output

53. The truth table for an S-R flip-flop has how many VALID entries?

1. 3
2. 1
3. 4
4. 2

54. What is one disadvantage of an S-R flip-flop?

1. It has no Enable input
2. It has a RACE condition
3. It has no clock input
4. It has only a single output

55. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

1. It can't be done
2. Invert the Q outputs
3. Invert the S-R inputs
4. None of the above

56. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

1. the clock pulse is LOW
2. the clock pulse is HIGH
3. the clock pulse transitions from LOW to HIGH
4. the clock pulse transitions from HIGH to LOW

57. What is the hold condition of a flip-flop?

1. Both S and R inputs activated
2. No active S or R input
3. Only S is active
4. Only R is active

58. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________?

1. SET
2. RESET
3. Clear
4. Invalid

59. What is one disadvantage of an S-R flip-flop?

1. It has no enable input
2. It has an invalid state
3. It has no clock input
4. It has only a single output

60. The terminal count of a 3-bit binary counter in the DOWN mode is ________?

1. 111
2. 101
3. 10