VLSI Design Multiple Choice Questions and Answers for Practice

16. Which of the following is not a common logic family used today?

1. RTL
2. ECL
3. TTL
4. CMOS

17. Which of the following is not a solution to interface problems between CMOS and TTL?

1. pull-up resistor
2. pull-down resistor
3. level-shifter
4. buffer

18. Which of the following levels would not be a valid LOW for a TTL gate?

1. 0.1 V
2. 0.7 V
3. 1.0 V
4. All are valid.

19. Which of the following output levels would be a valid HIGH for a TTL gate?

1. 3.0 V
2. 2.6 V
3. 5.1 V
4. All are valid.

20. Which of the following output levels would not be a valid LOW for a TTL gate?

1. 0.3 V
2. 0.5 V
3. 0.2 V
4. All are valid.

21. Which potential problem must be overcome when interfacing TTL to CMOS?

1. The HIGH output voltage may be too low.
2. The LOW output voltage may be too high.
3. The HIGH output voltage may be too high.
4. The output current may not be sufficient.

22. Which specialized device distinguishes the 74LSXX circuits from standard 74XX circuits?

1. a Schottky diode
2. a CMOS transistor
3. a multiemitter transistor
4. totem-pole output transistor

23. A common means for comparing the propagation delays and the power dissipation of various logic gates is the

1. fan-out.
2. power requirements.
3. speed-power product.
4. noise margin.

24. A family of logic devices designed for extremely high speed applications is called

1. NMOS
2. ECL
3. PMOS
4. TTL

25. An invalid input voltage for a TTL logic gate would be

1. less than 0.8 V.
2. greater than 2.0 V but less than 5.0 V.
3. greater than 2.0 V.
4. between 0.8 V and 2.0 V.

26. An open-collector TTL gate

1. must have an external pull-up resistor to produce a LOW.
2. must have an external pull-up resistor to produce a HIGH.
3. must have an external ground connected to the output to produce a LOW.
4. must have a transistor added to the output to produce a HIGH.

27. An open-collector TTL gate

1. can sink current but cannot source current.
2. can source current but cannot sink current.
3. cannot source or sink current.
4. can sink more current than a standard TTL gate.

28. Each input on a TTL gate is connected to the transistors

1. base.
2. collector.
3. gate.
4. emitter.

29. Fan-out for a typical TTL gate is

1. 10
2. 4
3. 54
4. 100

30. In order to interface an FPGA with an external device, you must set the value of the

1. sink current.
2. external power supply.
3. source current.
4. all of the above