VLSI Design Objective Questions | MCQ Quiz for Practice

61. The output stage of a TTL gate is a special design called a(n)

1. totem-pole.
2. DIP.
3. MSI.
4. multiemitter.

62. The primary advantage of ECL over TTL is that ECL integrated circuits have

1. very low power dissipation.
2. low noise margins.
3. very short propagation delay times.
4. both A and C

63. The propagation delay of standard TTL gates is approximately

1. 2 µsec.
2. 10 nsec.
3. 4 nsec.
4. 1 µsec.

64. The standard 74XX TTL IC family was originally developed in the

1. 1970s.
2. 1960s.
3. 1950s.
4. 1940s.

65. The time it takes for a square wave to go from 10% to 90% of its voltage level is called

1. fan-out.
2. rise time.
3. propagation delay.
4. fall time.

66. The time it takes for a square wave to go from 90% to 10% of its voltage level is called

1. rise time.
2. fan-out.
3. fall time.
4. propagation delay.

67. The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as

1. propagation delay.
2. rise time.
3. fan-out.
4. fall time.

68. The unused input for a NOR gate should be tied to

1. HIGH.
2. ground.
3. another unused input.
4. both B and C

69. The upper transistor of a totem-pole output is OFF when the gate output is

1. logic 1.
2. malfunctioning.
3. HIGH.
4. LOW.

70. The upper transistor of a totem-pole output is saturated when the gate output is

1. shorted.
2. HIGH.
3. logic 0.
4. LOW.

71. Typical TTL HIGH level output voltage is

1. 0.3 V.
2. 5.0 V.
3. 3.4 V.
4. 4.8 V.

72. Typical TTL LOW level output voltage is

1. 0.3 V.
2. 0.0 V.
3. 3.4 V.
4. 4.0 V.

73. Unused inputs on TTL, AND, and NAND gates

1. degrade the gates noise immunity.
2. if left open will have the same effect as HIGH inputs.
3. should be tied HIGH.
4. All of the above are correct.

74. What advantage does the 74HXX series device have over standard TTL?

1. reduced propagation delay
2. higher propagation delay
3. low power consumption
4. lower voltage requirements